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copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com cs5101a cs5102a 16-bit, 100 ksps / 20 ksps a/d converters features z monolithic cmos a/d converters ? inherent sampling architecture ? 2-channel input multiplexer ? flexible serial output port z ultra-low distortion ? s/(n+d): 92 db ? tdh: 0.001% z conversion time ? cs5101a: 8 s ? cs5102a: 40 s z linearity error: 0.001% fs ? guaranteed no missing codes z self-calibration maintains accuracy ? accurate over time & temperature z low power consumption ? cs5101a: 320 mw ? cs5102a: 44 mw description the cs5101a and cs5102a are 16-bit monolithic cmos analog-to-digital converters (adcs) capable of 100 ksps (5101a) and 20 ksps (5102a) throughput. the cs5102a?s low power consumption of 44mw, coupled with a power-down mode, makes it particularly suitable for battery-powered operation. on-chip self-calibration circuitry achieves nonlinearity of 0.001% of fs and guarantees 16-bit, no missing codes over the entire specified temperature range. superior lin- earity also leads to 92 db s/(n+d) with harmonics below -100 db. offset and full-scale errors are minimized dur- ing the calibration cycle, eliminating the need for external trimming. the cs5101a and cs5102a each consist of a 2-chan- nel input multiplexer, dac, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. the inherent sampling architec- ture of the device eliminates the need for an external track-and-hold amplifier. the converters? 16-bit data is output in serial form with either binary or two?s complement coding. three output timing modes are available for easy interfacing to micro- controllers and shift registers. unipolar and bipolar input ranges are digitally selectable ordering in formation see ?ordering information? on page 38 . i clkin refbuf vref ain1 agnd hold sleep rst code bp/up trk1 trk2 ssh/sdl sdata sclk test dgnd vd- vd+ va- va+ 12 28 2 5 16 17 8 9 11 15 3 21 20 19 22 25 23 7 1 6 26 14 - + - + - + - + clock generator control calibration microcontroller comparator 16-bit charge sram redistribution dac stby crs/fin 10 xout 4 ain2 24 ch1/2 13 sckmod 27 outmod 18 jan ?06 ds45f6
cs5101a cs5102a 2 ds45f6 table of contents 1. characteristics & specifi cations ........... ................ ............. ............. ............. ........... 4 analog characteristics, cs5101a............................................................................... 4 switching characteristics, cs5101a ......................................................................... 6 analog characteristics, cs5102a............................................................................... 7 switching characteristics, cs5102a ......................................................................... 9 switching characteristics, all devices ............................................................... 11 digital characteristics, all devices...................................................................... 13 recommended operating conditions ..................................................................... 13 absolute maximum ratings ...... ................ ................ ................ ............. ............. ......... 14 2. overview .................................................................................................................. ........... 15 3. theory of operation ..................................................................................................... 15 3.1 calibration ............................................................................................................... ......... 16 4. functional description ............................................................................................... 17 4.1 initiating conversions ............................. ....................................................................... ... 17 4.2 tracking the input ........................................................................................................ .... 17 4.3 master clock .............................................................................................................. ...... 18 4.4 asynchronous sampling considerations ......................................................................... 18 4.5 analog input range/coding format ................................................................................ 19 4.6 output mode control ....................................................................................................... .19 4.6.1 pipelined data transmission .............. ................................................................ 19 4.6.2 register burst transmission (rbt) .... ................................................................ 20 4.6.3 synchronous self-clocking (ssc) ....................................................................... 20 4.6.4 free run (frn) .................................................................................................. 20 5. system design using the cs5101a & cs5102a ......................................................... 22 5.1 system initialization ..................................................................................................... .... 22 5.2 single-channel operation ................................................................................................ 23 6. analog circuit connections ...................................................................................... 23 6.1 reference considerations .. ............................................................................................. 23 6.2 analog input connection ................................................................................................. 24 6.3 sleep mode operation ..................................................................................................... 2 4 6.4 grounding & power supply de coupling ........................................................................... 25 7. cs5101a & cs5102a performance ............................................................................... 26 7.1 differential nonlinearity ................................................................................................. ... 26 7.2 fft tests and windowing ............................................................................................... 28 7.3 sampling distortion ....................................................................................................... ... 30 7.4 noise ..................................................................................................................... ........... 31 7.5 aperture jitter ........................................................................................................... ....... 31 7.6 power supply rejection ................................................................................................... 3 2 8. pin descriptions .......................................................................................................... .... 33 8.1 power supply connections .............................................................................................. 33 8.2 oscillator ................................................................................................................ .......... 34 8.3 digital inputs ............................................................................................................ ........ 34 8.4 analog inputs ............................................................................................................. ...... 35 8.5 digital outputs ........................................................................................................... ...... 35 8.6 analog outputs ............................................................................................................ .... 35 8.7 miscellaneous ............................................................................................................. ..... 35 9. parameter definitions .................................................................................................. 36 10. package dimensions ..................................................................................................... 37 11. ordering information ................................................................................................ 38 12. environmental, manufacturing, & ha ndling information .......................... 38 13. revisions ............................................................................................................... ........... 39
cs5101a cs5102a ds45f6 3 list of figures figure 1. reset, calibration, and control timing .......................................................................... 10 figure 2. serial communication timing .............. .......................................................................... 12 figure 3. coarse charge input buffers & charge redistribution dac.......................................... 15 figure 4. coarse/fine charge control .......................................................................................... 1 8 figure 5. pipelined data transmission (pdt) mo de timing ......................................................... 20 figure 6. register burst transmission (rbt) mode timing.......................................................... 21 figure 7. synchronous self-clo cking (ssc) mode timing ............................................................ 21 figure 8. free run (frn) mode timing.............. .......................................................................... 21 figure 9. cs5101a/cs5102a system connection diagram......................................................... 22 figure 10. power-up re set circuit .............................................................................................. .. 23 figure 11. reference connections...................... ......................................................................... .24 figure 12. charge settling time ................................................................................................ ... 24 figure 13. cs5101a dnl plot - ambient temperature at 25 c .................................................. 27 figure 14. cs5101a dnl plot - ambient temperature at 138 c ................................................ 27 figure 15. cs5102a dnl plot - ambient temperature at 25 c .................................................. 27 figure 16. cs5102a dnl plot - ambient temperature at 138 c ................................................ 27 figure 17. cs5101a dnl error distribution.................................................................................. 28 figure 18. cs5102a dnl error distribution.................................................................................. 28 figure 19. cs5101a fft (ssc mode, 1-channel). ................ ................ ................ ............. ......... 29 figure 20. cs5101a fft (ssc mode, 1-channel). ................ ................ ................ ............. ......... 29 figure 21. cs5102a fft (ssc mode, 1-channel). ................ ................ ................ ............. ......... 29 figure 22. cs5102a fft (ssc mode, 1-channle). ................ ................ ................ ............. ......... 29 figure 23. cs5101a histogram plot of 8192 conv ersion inputs .................................................. 31 figure 24. cs5102a histogram plot of 8192 conv ersion inputs .................................................. 31 figure 25. power supply reject ion .............................................................................................. .32 figure 26. cs5101a & cs5102a 28-pin plcc pino ut ................................................................. 33 figure 27. 28-pin plcc mechanic al drawing............................................................................... 37 list of tables table 1. output coding ......................................................................................................... ........ 19 table 2. output mode control ................................................................................................... .... 19
cs5101a cs5102a 4 ds45f6 1. characteristics & specifications analog characteristics, cs5101a (ta = tmin to tmax; va+, vd+ = 5v; va-, vd - = -5v; vref = 4.5v; full- scale input sine wave, 1 khz; clkin = 8 mhz; fs = 100 ksps; bipolar mode; frn mode; ain1 and ain2 tied toget her, each channel tested separately; analog source impedance = 50 ? with 1000 pf to agnd unless otherwise specified) notes: 1. applies after calibration at any temperat ure within the specified temperature range. 2. total drift over specified temperature range after cali bration at power-up, at 25 o c. 3. minimum resolution for which no missing codes is guaranteed over the spec ified temperature range. 4. wideband noise aliased into the baseband, referred to the input. * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet. parameter* cs5101a-j cs5101a-b unit min typ max min typ max specified temperature range 0 to +70 -40 to +85 oc accuracy linearity error -j (note 1) -b drift (note 2) - - - 0.002 0.001 ? 0.003 0.002 - - - - 0.002 0.001 ? 0.003 0.002 - %fs %fs ? lsb differential linearity (note 3) 16 --16--bits full-scale error -j (note 1) -b drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 1 4 3 - lsb lsb ? lsb unipolar offset -j (note 1) -b drift (note 2) - - - 2 2 1 5 4 - - - - 2 2 1 5 4 - lsb lsb ? lsb bipolar offset -j (note 1) -b drift (note 2) - - - 2 2 1 5 3 - - - - 2 2 2 5 3 - lsb lsb ? lsb bipolar negative full-scale error -j (note 1) -b drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 1 4 3 - lsb lsb ? lsb dynamic performance (bipolar mode) peak harmonic or sp urious noise (note 1) 1-khz input -j -b 12-khz input -j -b 96 98 85 85 100 102 88 91 - - - - 96 98 85 85 100 102 88 91 - - - - db db db db total harmonic distortion -j -b - - 0.002 0.001 - - - - 0.002 0.001 - - % % signal-to-noise ratio (note 1) 0 db input -j -b -60 db input -j -b 87 90 - - 90 92 30 32 - - - - 87 90 - - 90 92 30 32 - - - - db db db db noise (note 4) unipolar mode bipolar mode - - 35 70 - - - - 35 70 - - v rms v rms
cs5101a cs5102a ds45f6 5 analog characteristics, cs5101a (continued) notes: 5. applies only in the track mode. when converting or calibrating, input capacitance will not exceed 30 pf. 6. conversion time scales directly to the master clock speed . the times shown are for synchronous, internal loopback (frn) mode) with 8.0 mhz clkin. in pdt, rbt, and ssc modes, asynchronous delay between the falling edge of hold and the start of conversion may add to the apparent conversion time. this delay will not exceed 1.5 master clock cycles + 10 ns. in pdt, rbt, an d ssc modes, clkin can be increased as long as the hold sample rate is 100 khz max. 7. the cs5101a requi res 6 clock cycles of coarse charge, followed by a mi nimum of 1.125 s of fine charge. frn mode allows 9 cycles for fine charge which provides for the minimum 1.125 s with an 8mhz clock, however; in pdt, rbt, or ssc modes and at clock frequencies of 8 mhz or less, fine ch arge may be less than 9 clock cycles. this reflects the typical specif ication (6 clock cycles + 1.125 s). 8. throughput is the sum of the acquisition and conversion times. it will vary in accordance with conditions affecting acquisition and conversion times, as described above. 9. all outputs unloaded. all inputs at vd+ or dgnd. 10. power consumption in the sleep mode applies with no master clock applied (clkin held high or low). 11. with 300 mv p-p, 1-khz ripple applied to each supply se parately in the bipolar mode. rejection improves by 6 db in the unipolar mode to 90 db. figure 25 shows a plot of typical power supply rejection versus frequency. parameter* symbol cs5101a-j cs5101a-b unit min typ max min typ max specified temperature range - 0 to +70 -40 to +85 oc analog input aperture time - - 25 - - 25 - ns aperture jitter - - 100 - - 100 - ps input capacitance (note 5) unipolar mode bipolar mode - - - - 320 200 425 265 - - 320 200 425 265 pf pf conversion and throughput conversion time (note 6) t c - - 8.12 - - 8.12 s acquisition time (note 7) t a - - 1.88 - - 1.88 s throughput (note 8) f tp 100 - - 100 - - ksps power supplies power supply current (note 9) positive analog negative analog (sleep high) positive digital negative digital i a + i a - i d + i d - - - - - 21 -21 11 -11 28 -28 15 -15 - - - - 21 -21 11 -11 28 -28 15 -15 ma ma ma ma power consumption (note 9, note 10) (sleep high) (sleep low) p do p ds - - 320 1 430 - - - 320 1 430 - mw mw power supply rejection (note 11) positive supplies negative supplies psr psr - - 84 84 - - - - 84 84 - - db db
cs5101a cs5102a 6 ds45f6 switching character istics, cs5101a (ta = tmin to tmax; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 50 pf). notes: 12. external loading capacitors are required to allow the cr ystal to oscillate. maximum cr ystal frequency is 8.0 mhz in frn mode (100 ksps). 13. with an 8.0 mhz crystal, two 10 pf loading capacitors and a 10 m ? parallel resistor (see figure 9). 14. these timings are for frn mode. 15. ssh only works correctly if hold falling edge is within +15 to +30 ns of ch1/2 edge or if ch1/2 edge occurs after hold rises to 64t clk after hold has fallen. these timings are for pdt and rbt modes. 16. when hold goes low, the analog sample is captur ed immediately. to start conversion, hold must be latched by a falling edge of cllkin. conversion will beg in on the next rising edge of clkin after hold is latched. if hold is operated synchronous to clkin, the hold pulse width may be as narrow as 150 ns for all clkin frequencies if clkin falls 95 ns after hold falls. this ensures that the hold pulse will meet the minimum specification for t hcf . parameter symbol min typ max unit clkin period t clk 108 - 10,000 ns clkin low time t clkl 37.5 - - ns clkin high time t clkh 37.5 - - ns crystal frequency (note 12) f xtal 2.0 - 9.216 mhz sleep rising to oscillato r stable (note 13) - - 2 - ms rst pulse width t rst 150 - - ns rst to stby falling t drrs -100 -ns rst rising to stby rising t cal - 11,528,160 - t clk ch1/2 edge to trk1, trk2 rising (note 14) t drsh1 -80 -ns ch1/2 edge to trk1, trk2 falling (note 14) t dfsh4 --68t clk +260 ns hold to ssh falling (note 15) t dfsh2 -60 -ns hold to trk1, trk2 falling (note 15) t dfsh1 66t clk -68t clk +260 ns hold to trk1, trk2, ssh rising (note 15) t drsh -120 -ns hold pulse width (note 16) t hold 1t clk +20 - 63t clk ns hold to ch1/2 edge (note 15) t dhlri 15 - 64t clk ns hold falling to clkin falling (note 16) t hcf 95 - 1t clk +10 ns
cs5101a cs5102a ds45f6 7 analog characteristics, cs5102a (ta = tmin to tmax; va+, vd+ = 5v; va-, vd- = -5v; vref = 4.5v; full-scale input sine wa ve, 200 hz; clkin = 1.6 mhz; fs = 20 ksps; bipolar mode; frn mode; ain1 and ain2 tied together, each ch annel tested separately; analog source impedance = 50 ? with 1000 pf to agnd unless otherwise specified) * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet. parameter* cs5102a-j cs5102a-b unit min typ max min typ max specified temperature range 0 to +70 -40 to +85 oc accuracy linearity error -j (note 1) -b drift (note 2) - - - 0.002 0.001 ? 0.003 0.0015 - - - - 0.002 0.001 ? 0.003 0.0015 - %fs %fs ? lsb differential linearity (note 3) 16 --16- -bits full-scale error -j (note 1) -b drift (note 2) - - - 2 2 1 4 3 - - - - 2 2 1 4 3 - lsb lsb ? lsb unipolar offset -j (note 1) -b drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 1 4 3 - lsb lsb ? lsb bipolar offset -j (note 1) -b drift (note 2) - - - 1 1 1 4 3 - - - - 1 1 2 4 3 - lsb lsb ? lsb bipolar negative full-scale error -j (note 1) -b drift (note 2) - - - 2 2 1 4 3 - - - - 2 2 2 4 3 - lsb lsb ? lsb dynamic performance (bipolar mode) peak harmonic or sp urious noise (note 1) -j -b 96 98 100 102 - - 96 98 100 102 - - db db total harmonic distortion -j -b - - 0.002 0.001 - - - - 0.002 0.001 - - % % signal-to-noise ratio (note 1) 0 db input -j -b -60 db input -j -b 87 90 - - 90 92 30 32 - - - - 87 90 - - 90 92 30 32 - - - - db db db db noise (note 4) unipolar mode bipolar mode - - 35 70 - - - - 35 70 - - v rms v rms
cs5101a cs5102a 8 ds45f6 analog characteristics, cs5102a (continued) notes: 17. conversion time scales directly to the master clock speed . the times shown are for synchronous, internal loopback (frn) mode. in pdt, rbt, and ssc modes, asynchronous delay between the falling edge of hold and the start of conversion may add to t he apparent conversion time. this delay will not exceed 1 master clock cycle + 140 ns. 18. the cs5102a requi res 6 clock cycles of coarse charge, followed by a mi nimum of 5.625 s of fine charge. frn mode allows 9 cycles for fine charge which provides for the minimum 5.625 s with a 1.6 mhz clock, however; in pdt, rbt, or ssc modes and at clo ck frequencies of less than 1.6 mhz, fi ne charge may be less than 9 clock cycles. 19. throughput is the sum of the acquisition and conversion times. it will vary in accordance with conditions affecting acquisition and conversion times, as described above. 20. all outputs unloaded. all inputs at vd+ or dgnd. see table below for power dissipation versus clock frequency. 21. with 300 mv p-p, 1-khz ripple applied to each supply se parately in the bipolar mode. rejection improves by 6 db in the unipolar mode to 90 db. figure 25 shows a plot of typical power supply rejection versus frequency. parameter* symbol cs5102a-j cs5102-b unit min typ max min typ max specified temperature range - 0 to +70 -40 to +85 oc analog input aperture time - - 30 - - 30 - ns aperture jitter - - 100 - - 100 - ps input capacitance (note 5) unipolar mode bipolar mode - - - - 320 200 425 265 - - 320 200 425 265 pf pf conversion and throughput conversion time (note 17) t c - - 40.625 - - 40.625 s acquisition time (note 18) t a - - 9.375 - - 9.375 s throughput (note 19) f tp 20 - - 20 - - ksps power supplies power supply current (note 20) positive analog negative analog (sleep high) positive digital negative digital i a + i a - i d + i d - - - - - 2.4 -2.4 2.5 -1.5 3.5 -3.5 3.5 -2.5 - - - - 2.4 -2.4 2.5 -1.5 3.5 -3.5 3.5 -2.5 ma ma ma ma power consumption (note 10, note 20) (sleep high) (sleep low) p do p ds - - 44 1 65 - - - 44 1 65 - mw mw power supply rejection (note 21) positive supplies negative supplies psr psr - - 84 84 - - - - 84 84 - - db db typical power (mw) clkin (mhz) 34 0.8 37 1.0 39 1.2 41 1.4 44 1.6
cs5101a cs5102a ds45f6 9 switching character istics, cs5102a (ta = tmin to tmax; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 50 pf). notes: 22. minimum clkin period is 0.625 ms in frn mode (20 ksps). 23. external loading capacitors are required to allow the cr ystal to oscillate. maximum cr ystal frequency is 1.6 mhz in frn mode (20 ksps). 24. with a 2.0 mhz crystal, two 33 pf loading capacitors and a 10 m ? parallel resistor (see figure 9). 25. these timings are for frn mode. 26. ssh only works correctly if hold falling edge is within +15 to +30 ns of ch1/2 edge or if ch1/2 edge occurs after hold rises to 64t clk after hold has fallen. these timings are for pdt and rbt modes. 27. when hold goes low, the analog sample is captur ed immediately. to start conversion, hold must be latched by a falling edge of cllkin. conversion will beg in on the next rising edge of clkin after hold is latched. if hold is operated synchronous to clkin, the hold pulse width may be as narrow as 150 ns for all clkin frequencies if clkin falls 55 ns after hold falls. this ensures that the hold pulse will meet the minimum specification for t hcf . parameter symbol min typ max unit clkin period (note 22) t clk 0.5 - 10 s clkin low time t clkl 200 - - ns clkin high time t clkh 200 - - ns crystal frequency (note 22, note 23) f xtal 0.9 1.6 2.0 mhz sleep rising to oscillato r stable (note 24) - - 20 - ms rst pulse width t rst 150 - - ns rst to stby falling t drrs -100 -ns rst rising to stby rising t cal - 2,882,040 - t clk ch1/2 edge to trk1, trk2 rising (note 25) t drsh1 -80 -ns ch1/2 edge to trk1, trk2 falling (note 25) t dfsh4 --68t clk +260 ns hold to ssh falling (note 26) t dfsh2 -60 -ns hold to trk1, trk2 falling (note 26) t dfsh1 66t clk -68t clk +260 ns hold to trk1, trk2, ssh rising (note 26) t drsh -120 -ns hold pulse width (note 27) t hold 1t clk +20 - 63t clk ns hold to ch1/2 edge (note 26) t dhlri 15 - 64t clk ns hold falling to clkin falling (note 27) t hcf 55 - 1t clk +10 ns
cs5101a cs5102a 10 ds45f6 figure 1. reset, calibration, and control timing dhlri t hold t ch1/2 hold clkin t hcf hold rst t cal t drrs t rst stby dfsh4 t ch1/2 drsh1 t hold ssh,trk1,trk2 dfsh2 t drsh t dfsh1 t trk1,trk2 trk1,trk2 trk1,trk2 ssh/sdl reset and calibration timing a. frn mode b. pdt, rbt mode channel selection timing start conversion timing control output timing
cs5101a cs5102a ds45f6 11 switching characteris tics, all devices (ta = tmin to tmax; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 50 pf). notes: 28. only valid for trk1 , trk2 falling when sclk is low. if sclk is high when trk1 , trk2 falls, then sdata is valid t dss time after the next falling sclk. parameter symbol min typ max unit pdt & rbt modes sclk input pulse period t sclk 200 - - ns sclk input pulse width low t sclkl 50 - - ns sclk input pulse width high t sclkh 50 - - ns sclk input falling to sdata valid t dss -100150ns hold falling to sdata valid pdt mode t dhs -140230ns trk1, trk2 falling to sdata valid (note 28) t dts -65125ns frn & ssc modes sclk output pulse width low t slkl -2t clk -t clk sclk output pulse width high t slkh -2t clk -t clk sdata valid before rising sclk t ss 2t clk -100 - - ns sdata valid after rising sclk t sh 2t clk -100 - - ns sdl falling to 1 st rising sclk t rsclk 66t clk 2t clk 68t clk +260 ns last rising sclk to sdl rising cs5101a cs5102a t rsdl t rsdl - - 2t clk 2t clk 2t clk +165 2t clk +200 ns hold falling to 1 st falling sclk cs5101a cs5102a t hfs t hfs 6t clk 6t clk - - 8t clk +165 8t clk +200 ns ch1/2 edge to 1 st falling sclk t dhlri -7t clk 64t clk t clk
cs5101a cs5102a 12 ds45f6 figure 2. serial communication timing sclkl t sclkh t dss t sdata sclk sclk msb dhs t hold sdata msb sdata dts t sclk t dss t msb-1 sclk trk1, trk2 ss t msb sclk sh t sdata slkh t slkl t dss t chfs t ch1/2 hold hfs t ssh/sdl rsclk t lsb rsdl t a. sclk input (pdt & rbt modes) b. sclk ou tput (frn & ssc modes) a. pipelined data transmission (pdt) b . register burst transmission (rbt) serial data timing data transmission timing
cs5101a cs5102a ds45f6 13 digital characteristics, all devices (ta = tmin to tmax; va+, vd+ = 5v 10%; va-, vd- = -5v 10% 29. va- and vd- can be any value from 0 to +5v for memory retention. neither va- nor vd- should be allowed to go positive. ain1, ain2, or vref must not be greater than va+ or vd+. this parameter is guaranteed by characterization. 30. i out = -100 a. this specification guar antees ttl compatibility (v oh = 2.4v @ i out = -40 a). recommended operating conditions (agnd, dgnd = 0v, see note 31) 31. all voltages with respect to ground. 32. the cs5101a and cs5102a can accept input voltages up to the analog supplies (va+ and va-). they will produce an output of all 1s for input above vref and all 0s for inputs below agnd in unipolar mode, and -vref in bipolar mode, with binary coding (code = low). parameter symbol min typ max unit calibration memory retention (note 29) power supply voltage va+ and vd+ v mr 2.0 - - v high-level input voltage v ih 2.0 - - v low-level input voltage v il --0.8v high-level output voltage (note 30) v oh (vd+) -1.0 - - v low-level output voltage (except xout) i out = 1.6 ma v ol --0.4v input leakage current i in --10a digital output pin capacitance c out -9-pf parameter symbol min typ max unit dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 va+ -5.5 5.5 -5.5 v v v v analog reference voltage vref 2.5 4.5 (va+)-0.5 v dc power supplies: (note 32) unipolar bipolar v ain v ain agnd -vref - - vref vref v v
cs5101a cs5102a 14 ds45f6 absolute maximum ratings (agnd, dgnd = 0v, all voltages with respect to ground. ) notes: 33. in addition, vd+ must not be greater than (va+) + 0.3 v. 34. transient currents of up to 1 00 ma will not cause scr latch-up warning: operation beyond these limits may result in permanent damage to the device. parameter symbol min typ max unit dc power supplies: (note 33) positive digital negative digital positive analog negative analog vd+ vd- va+ va- -0.3 0.3 -0.3 0.3 - - - 6.0 -6.0 6.0 -6.0 v v v v input current, any pin ex cept supplies (note 34) i in --10ma analog input voltage (ain and vref pins) v ina (va-) - 0.3 - (va+) + 0.3 v digital input voltage v ind -0.3 - (va+) + 0.3 v ambient operating temperature t a -55 - 125 c storage temperature t stg -65 - 150 c
cs5101a cs5102a ds45f6 15 2. overview the cs5101a and cs5102a are 2-channel, 16-bit a/d converters. the devices include an inherent sample/hold and an on-chip analog switch for 2- channel operation. both channels can thus be sampled and converted at rates up to 50 ksps each (cs5101a) or 10 ksps each (cs5102a). al- ternatively, each of the devices can be operated as a single channel adc operating at 100 ksps (cs5101a) or 20 ksps (cs5102a). both the cs5101a and cs5102a can be config- ured to accept either unipolar or bipolar input rang- es, and data is output serially in either binary or 2's complement coding. the devices can be config- ured in 3 different output modes, as well as an in- ternal, synchronous loopback mode. the cs5101a and cs5102a provide coarse charge/fine charge control, to allow accurate track- ing of high-slew signals. 3. theory of operation the cs5101a and cs5102a implement the suc- cessive approximation algorithm using a charge redistribution architecture. instead of the traditional resistor network, the dac is an array of binary- weighted capacitors. all capacitors in the array share a common node at the comparator's input. as shown in figure 3, their other terminals are ca- pable of being connected to agnd, vref, or ain (1 or 2). when the device is not calibrating or con- verting, all capacitors are tied to ain. switch s1 is closed and the charge on the array, tracks the in- put signal. when the conversion command is issued, switch s1 opens. this traps the charge on the comparator side of the capacitor array and creates a floating node at the comparator's input. the conversion al- gorithm operates on this fixed charge, and the sig- nal at the analog input pin is ignored. in effect, the entire dac capacitor array serves as analog mem- ory during conversion much like the hold capacitor in a sample/hold amplifier. the conversion consists of manipulating the free plates of the capacitor array to vref and agnd to form a capacitive divider. since the charge at the floating node remains fixed, the voltage at that point depends on the proportion of capacitance tied to vref versus agnd. the successive ap- proximation algorithm is used to find the proportion of capacitance, which when connected to the refer- ence will drive the voltage at the floating node to zero. that binary fraction of capacitance repre- sents the converter's digital output. figure 3. coarse charge input buffers & charge redistribution dac ain c c/2 c/32,768 m s b lsb bit 15 bit 14 bit 13 bit 0 c = c + c/2 + c/4 + c/8 + ... c/32,768 tot dummy c/32,768 s1 c/4 fine vref agnd coarse coarse fine coarse fine + - + - + - + -
cs5101a cs5102a 16 ds45f6 3.1 calibration the ability of the cs5101a or the cs5102a to con- vert accurately to 16-bits clearly depends on the accuracy of its comparator and dac. each device utilizes an ?auto-zeroing? scheme to null errors in- troduced by the comparator. all offsets are stored on the capacitor array while in the track mode and are effectively subtracted from the input signal when a conversion is initiated. auto-zeroing en- hances power supply rejection at frequencies well below the conversion rate. to achieve 16-bit accuracy from the dac, the cs5101a and cs5102a use a novel self-calibra- tion scheme. each bit capacitor shown in figure 3 actually consists of several capacitors in parallel which can be manipulated to adjust the overall bit weight. an on-chip microcontroller precisely ad- justs each capacitor with a resolution of 18 bits. the cs5101a and cs5102a should be reset upon power-up, thus initiating a calibration cycle. the device then stores its calibration coefficients in on- chip sram. when the cs5101a and cs5102a are in power-down mode (sleep low), they retain the calibration coefficients in memory, and need not be recalibrated when normal operation is resumed.
cs5101a cs5102a ds45f6 17 4. functional description monolithic design and inherent sampling architec- ture make the cs5101a and cs5102a extremely easy to use. 4.1 initiating conversions a falling transition on the hold pin places the in- put in the hold mode and initiates a conversion cy- cle. the charge is trapped on the capacitor array the instant hold goes low. the device will com- plete conversion of the sample within 66 master clock cycles, then automatic ally return to the track mode. after allowing a short time for acquisition, the device will be ready for another conversion. in contrast to systems with separate track-and- holds and a/d converters, a sampling clock can simply be connected to the hold input. the duty cycle of this clock is not critical. the hold input is latched internally by the master clock, so it need only remain low for 1/f clk + 20 ns, but no longer than the minimum conversion time minus two mas- ter clocks or an additional conversion cycle will be initiated with inadequate time for acquisition. in free run mode, sckmod = outmod = 0, the device will convert at a rate of clkin/80, and the hold input is ignored. as with any high-resolution a-to-d system, it is rec- ommended that sampling is synchronized to the master system clock in order to minimize the ef- fects of clock feed through. however, the cs5101a and cs5102a may be operated entirely asynchronous to the master clock if necessary. 4.2 tracking the input upon completing a conversion cycle the cs5101a and cs5102a immediately return to the track mode. the ch1/2 pin directly controls the input switch, and therefore directly determines which channel will be tracked. ideally, the ch1/2 pin should be switched during the conversion cycle, thereby nullifying the input mux switching time, and guaranteeing a stable input at the start of acquisi- tion. if, however, the ch1/2 control is changed dur- ing the acquisition phase, adequate coarse charge and fine charge time must be allowed before initi- ating conversion. when the cs5101a or the cs5102a enters track- ing mode, it uses an internal input buffer amplifier to provide the bulk of the charge on the capacitor array (coarse-charge), thereby reducing the cur- rent load on the external analog circuitry. coarse- charge is internally initiated for 6 clock cycles at the end of every conversion. the buffer amplifier is then bypassed, and the capacitor array is directly connected to the input. this is referred to as fine- charge, during which the charge on the array is al- lowed to accurately settle to the input voltage (see figure 12). with a full-scale input step, the coarse-charge in- put buffer of the cs5101a will charge the capacitor array within 1% in 650 ns. the converter timing al- lows 6 clock cycles for co arse charge settling time. when the cs5101a switches to fine-charge mode, its slew rate is somewhat reduced. in fine-charge, the cs5101a can slew at 2 v/ s in unipolar mode. in bipolar mode, only half the capacitor array is connected to the analog input, so the cs5101a can slew at 4v/ s. with a full-scale input step, the coarse-charge in- put buffer of the cs5102a will charge the capacitor array within 1% in 3.75 s. the converter timing al- lows 6 clock cycles for co arse charge settling time. when in fine-charge mode, the cs5102a can slew at 0.4 v/ s in unipolar mode; and at 0.8 v/ s in bi- polar mode. acquisition of fast slewing signals can be hastened if the voltage change occurs during or immediately following the conversion cycle. for instance, in multiple channel applications (using either the de- vice's internal channel selector or an external mux), channel selection should occur while the cs5101a or the cs5102a is converting. multiplex- er switching and settling time is thereby removed from the overall throughput equation. if the input signal changes drastically during the acquisition period (such as changing the signal source), the device should be in coarse-charge for an adequate period following the change. the cs5101a and cs5102a can be forced into coarse- charge by bringing crs/fin high. the buffer am- plifier is engaged when crs/fin is high, and may be switched in any number of times during track- ing. if crs/fin is held low, the cs5101a and cs5102a will only coarse-charge for the first 6 clock cycles following a c onversion, and will stay in
cs5101a cs5102a 18 ds45f6 fine-charge until hold goes low. to get an accu- rate sample using the cs5101a, at least 750 ns of coarse-charge, followed by 1.125 s of fine-charge is required before initiating a conversion. if coarse charge is not invoked, then up to 25 s should be allowed after a step change input for proper acqui- sition. to get an accurate sample using the cs5102a, at least 3.75 s of coarse-charge, fol- lowed by 5.625 s of fine-charge is required before initiating a conversion (see figure 4). if coarse charge is not invoked, then up to 125 s should be allowed after a step change input for proper acqui- sition. the crs/fin pin must be low prior to hold becoming active and be held low during conver- sion. figure 4. coarse/f ine charge control 4.3 master clock the cs5101a and cs5102a can operate either from an externally-supplied master clock, or from their own crystal oscillator (with a crystal). to en- able the internal crystal oscillator, simply tie a crys- tal across the xout and clkin pins and add 2 capacitors and a resistor , as shown on the system connection diagram in figure 9. calibration and conversion times directly scale to the master clock frequency. the cs5101a can op- erate with clock or crystal frequencies up to 9.216 mhz (8.0 mhz in frn mode). this allows maxi- mum throughput of up to 50 ksps per channel in dual-channel operation, or 100 ksps in a single- channel configuration. the cs5102a can operate with clock or crystal frequencies up to 2.0 mhz (1.6 mhz in frn mode). this allows maximum throughput of up to 10 ksps per channel in dual- channel operation, or 20 ksps in a single channel configuration. for 16-bit performance a 1.6 mhz clock is recommended. this 1.6 mhz clock yields a maximum throughput of 20 ksps in a single- channel configuration. 4.4 asynchronous sampling considerations when hold goes low, the analog sample is cap- tured immediately. the hold signal is latched by the next falling edge of clkin, and conversion then starts on the subsequent rising edge. if hold is asynchronous to clkin, then there will be a 1.5- clkin-cycle uncertainty as to when conversion starts. considering the cs5101a with an 8 mhz clkin, with a 100 khz hold signal, then this 1.5- clkin uncertainty will result in a 1.5-clkin-period possible reduction in fine charge time for the next conversion. this reduced fine charge time will be less than the minimum specification. if the clkin frequency is increased slightly (for example, to 8.192 mhz) then sufficient fine charge time will always occur. the maximum frequency for clkin is specified at 9.216 mhz. it is recommended that for asynchro- nous operation at 100 ksps, clkin should be be- tween 8.192 mhz and 9.216 mhz. clkin crs/fin internal status conv. coarse fine chg. coarse fine chg. conv. trk1 or trk2 hold min: 1.125 s* 6 clk 2 clk min: 750 ns* 3.75 s** 5.625 s** * applies to 5101a ** applies to 5102a
cs5101a cs5102a ds45f6 19 4.5 analog input range/coding format the reference voltage directly defines the input voltage range in both the unipolar and bipolar con- figurations. in the uni polar configuration (bp/up low), the first code transition occurs 0.5 lsb above agnd, and the final code transition occurs 1.5 lsbs below vref. in the bipolar con- figuration (bp/up high), the first code transition oc- curs 0.5 lsb above -vref and the last transition occurs 1.5 lsbs below +vref. the cs5101a and cs5102a can output data in either 2's comple- ment, or binary format. if the code pin is high, the output is in 2's complement format with a range of -32,768 to +32,767. if the code pin is low, the out- put is in binary format with a range of 0 to +65,535. see table 1 for output coding. 4.6 output mode control the cs5101a and cs5102a can be configured in three different output modes, as well as an internal, synchronous loop-back mode. this allows great flexibility for design into a wide variety of systems. the operating mode is selected by setting the states of the sckmod and outmod pins. in all modes, data is output on sd ata, starting with the msb. each subsequent data bit is updated on the falling edge of sclk. when sckmod is high, sclk is an input, allowing the data to be clocked out with an external serial clock at rates up to 5 mhz. additional clock edges after #16 will clock out logic 1s on sdata. tying sckmod low reconfigures sclk as an output, and the converter clocks out each bit as it is deter- mined during the conversion process, at a rate of 1/4 the master clock speed. table 2 shows an overview of the different states of sckmod and outmod, and the corresponding output modes. 4.6.1 pipelined data transmission pdt mode is selected by tying both sckmod and outmod high. in pdt m ode, the sclk pin is an input. data is registered during conversion, and output during the following conversion cycle. hold must be brought low, initiating another con- version, before data from the previous conversion is available on sdata. if all the data has not been clocked out before the next falling edge of hold , the old data will be lost (figure 5). table 1. output coding unipolar input voltage offset binary two?s complement bipolar input voltage >(vref-1.5 lsb) ffff 7fff >(vref-1.5 lsb) vref-1.5 lsb ffff fffe 7fff 7ffe vref-1.5 lsb (vref/2)-0.5 lsb 8000 7fff 0000 ffff -0.5 lsb +0.5 lsb 0001 0000 8001 8000 -vref+0.5 lsb <(+0.5 lsb) 0000 8000 <(-vref+0.5 lsb) table 2. output mode control mode sckmod outmod sclk ch1/2 hold pdt 1 1 input input input rbt 1 0 input input input ssc 0 1 output input input frn 0 0 output output x
cs5101a cs5102a 20 ds45f6 4.6.2 register burst transmission (rbt) rbt mode is selected by tying sckmod high, and outmod low. as in pdt mode, sclk is an input, however data is avail able immediately following conversion, and may be clocked out the moment trk1 or trk2 falls. the falling edge of hold clears the output buffer, so any unread data will be lost. a new conversion may be initiated before all the data has been clocked out if the unread data bits are not important (figure 6). 4.6.3 synchronous self-clocking (ssc) ssc mode is selected by tying sckmod low, and outmod high. in ssc mode, sclk is an output, and will clock out each bit of the data as it's being converted. sclk will remain high between conver- sions, and run at a rate of 1/4 the master clock speed for 16 low pulses during conversion (figure 7). the ssh/sdl goes low coincident with the first falling edge of sclk, and returns high 2 clkin cy- cles after the last rising edge of sclk. this signal frames the 16 data bits and is useful for interfacing to shift registers (e.g. 74hc595) or to dsp serial ports. 4.6.4 free run (frn) free run is the internal, synchronous loopback mode. frn mode is selected by tying sckmod and outmod low. sclk is an output, and oper- ates exactly the same as in the ssc mode. in free run mode, the converter initiates a new conver- sion every 80 master clock cycles, and alternates between channel 1 and channel 2. hold is dis- abled, and should be tied to either vd+ or dgnd. ch1/ 2 is an output, and will change at the start of each new conversion cycle, indicating which chan- nel will be tracked after the current conversion is finished (figure 8). the ssh/sdl goes low coincident with the first falling edge of sclk, and returns high 2 clkin cy- cles after the last rising edge of sclk. this signal frames the 16 data bits and is useful for interfacing to shift registers (e.g. 74hc595) or to dsp serial ports. figure 5. pipelined data transmission (pdt) mode timing clkin (i) hold (i) internal status sclk (i) sdata (o) ch1/2 (i) d15 d14 d1 d0 (ch. 1) trk1 (o) trk2 (o) ssh/sdl (o) converting ch. 2 d15 d14 d1 d0 (ch. 2) converting ch. 1 d15 68 72 76 048 64687276 48 64 60 60 0 0 tracking ch. 1 tracking ch. 2
cs5101a cs5102a ds45f6 21 figure 6. register burst transmission (rbt) mode timing figure 7. synchronous self -clocking (ssc) mode timing figure 8. free run (frn) mode timing clkin (i) hold (i) internal status sclk (i) sdata (o) ch1/2 (i) trk1 (o) trk2 (o) ssh/sdl (o) converting ch. 2 converting ch. 1 d0 d0 channel 2 data channel 1 data 04 4 0 0 64 68 72 64 68 72 tracking c h. 1 tracking c h. 2 d15 d14 d1 d0 (ch. 1) clkin (i) hold (i) internal status sclk (o) sdata (o) ch1/2 (i) d15 d14 d1 d0 (ch. 2) trk1 (o) trk2 (o) ssh/sdl (o) 68 72 76 048 64 68 72 76 4 864 0 0 6 6 converting ch. 2 tracking ch. 1 converting ch. 1 tracking ch. 2 c lkin (i) d15 d1 d0 (ch. 1) internal status sclk (o) sdata (o) ch1/2 (o) d15 d1 d0 (ch. 2) trk1 (o) trk2 (o) ssh/sdl (o) 68 72 76 048 64 68 72 76 4 8 64 0 0 7 69 7 69 converting ch. 2 tracking c h. 1 converting ch. 1 tracking ch. 2
cs5101a cs5102a 22 ds45f6 5. system design usin g the cs5101a & cs5102a figure 9 shows a general system connec tion diagram for the cs5101a and cs5102a. figure 9. cs5101a/cs5102a system connection diagram 5.1 system initialization upon power up, the cs5101a and cs5102a must be reset to guarantee a consistent starting condi- tion and to initially calibrate the device. due to each device's low power dissipation and low tem- perature drift, no warm-up time is required before reset to accommodate any self-heating effects. however, the voltage reference input should have stabilized to within 0.25% of its final value before rst rises to guarantee an accurate calibration. later, the cs5101a and cs5102a may be reset at any time to initiate a single full calibration. when rst is brought low all internal logic clears. when rst returns high on the cs5101a, a cali- bration cycle begins which takes 11,528,160 mas- ter clock cycles to complete (approximately 1.4 seconds with an 8 mhz master clock). the cal- ibration cycle on the cs5102a takes 2,882,040 master clock cycles to complete (approximately 1.8 seconds with a 1.6 mhz master clock). the cs5101a's and cs5102a's stby output remains low throughout the calibration sequence, and a ris- ing transition indicates the device is ready for nor- mal operation. while calibrating, the cs5101a and cs5102a will ignore changes on the hold input. to perform the reset function, a simple power-on reset circuit can be built using a resistor and ca- pacitor as shown in figure 10. the resistor should be less than or equal to 10 k ? . the system power supplies, voltage reference, and clock should all be established prior rst rising. va+ vd+ 10 +5va + 4.7 f 0.1 f + 1 f 0.1 f 23 1 10 ++ -5va 4.7 f 0.1 f1 f 0.1 f 0.1 f 21 va- vd- refbuf 25 7 clkin xout 6 dgnd sleep stby trk1 trk2 ssh/sdl sdata rst ch1/2 sclk hold 10 m 3 4 ext clock c2 = c1 10 28 5 8 9 11 15 2 13 14 12 data interface control logic crs/fin 16 17 27 18 26 code sckmod outmod bp/up vd+ mode control ain1 ain2 19 24 50 1 nf 50 1 nf analog sources vref agnd 20 22 voltage reference * * * for best dynamic s/(n+d) performance. npo npo unused logic inputs should be tied to vd+ or dg nd . c1 cs5101a or cs5102a xtal xtal & c1 table cs5101a frn cs5102a frn xtal 8.0 mhz 8.192 mhz 1.6 mhz c1, c2 10 pf 10 pf 30 pf 30 pf 2.0 mhz 1.6 mhz or tst pdt, rbt, ssc pdt, rbt, ssc c0g c0g
cs5101a cs5102a ds45f6 23 figure 10. power- up reset circuit 5.2 single-channel operation the cs5101a and cs5102a can alternatively be used to sample one channel by tying the ch1/2 in- put high or low. the unused ain pin should be tied to the analog input signal or to agnd. (if operating in free run mode, ain1 and ain2 must be tied to the same source, as ch1/2 is reconfigured as an output.) 6. analog circuit connections most popular successive approximation a/d con- verters generate dynamic loads at their analog connections. the cs5101a and cs5102a inter- nally buffer all analog inputs (ain1, ain2, vref, and agnd) to ease the demands placed on exter- nal circuitry. however, accurate system operation still requires careful attention to details at the de- sign stage regarding source impedances as well as grounding and decoupling schemes. 6.1 reference considerations an application note titled an004, voltage references for the cs5012a / cs5014 /cs5016 / cs5101a/ cs5102a / cs5126 series of a/d con verters is available for the cs5101a and cs5102a. in addition to working through a refer- ence circuit design example, it offers several built- and-tested reference circuits. during conversion, each capacitor of the calibrated capacitor array is switched between vref and agnd in a manner determined by the successive- approximation algorithm. the charging and dis- charging of the array results in a current load at the reference. the cs5101a and cs5102a each in- clude an internal buffer amplifier to minimize the external reference circuit's drive requirement and preserve the reference's integrity. whenever the array is switched during conversion, the buffer is used to coarse-charge the array thereby providing the bulk of the necessary charge. the appropriate array capacitors are then switched to the unbuf- fered vref pin to avoid any errors due to offsets and/or noise in the buffer. the external reference circuitry need only provide the residual charge required to fully charge the ar- ray after coarse-charging from the buffer. this cre- ates an ac current load as the cs5101a and cs5102a sequence through conversions. the ref- erence circuitry must have a low enough output im- pedance to drive the requisite current without changing its output voltage significantly. as the an- alog input signal varies, the switching sequence of the internal capacitor array changes. the current load on the external reference circuitry thus varies in response with the analog input. therefore, the external reference must not exhibit significant peaking in its output impedance characteristic at signal frequencies or their harmonics. a large capacitor connected between vref and agnd can provide sufficiently low output imped- ance at the high end of the frequency spectrum, while almost all precisi on references exhibit ex- tremely low output impedance at dc. the pres- ence of large capacitors on the output of some voltage references, however, may cause peaking in the output impedance at intermediate frequen- cies. care should be exerci sed to ensure that sig- nificant peaking does not exist or that some form of compensation is provided to eliminate the effect. the magnitude of the current load on the external reference circuitry will scale to the master clock fre- quency. at the full-rated 9.216 mhz clock (cs5101a), the reference must supply a maximum load current of 20 a peak-to-peak (2 a typical). an output impedance of 2 ? will therefore yield a maximum error of 40 v. at the full-rated 2.0 mhz clock (cs5102a), the reference must supply a maximum load current of 5 a peak-to-peak (0.5 a typical). an output impedance of 2 ? will therefore yield a maximum error of 10.0 v. with a 4.5 v reference and lsb size of 138 v this would ensure approximately 1/14 lsb accuracy. a 10 f vd+ rst cs5101a or cs5102a r c 1n4148 +5v
cs5101a cs5102a 24 ds45f6 capacitor exhibits an impedance of less than 2 ? at frequencies greater than 16 khz. a high-quality tantalum capacitor in parallel with a smaller ceram- ic capacitor is recommended. peaking in the reference's output impedance can occur because of capacitive loading at its output. any peaking that might occur can be reduced by placing a small resistor in series with the capaci- tors. the equation in figure 11 can be used to help calculate the optimum value of r for a particular reference. the term ?f peak ? is the frequency of the peak in the output impedance of the reference be- fore the resistor is added. figure 11. reference connections the cs5101a and cs5102a can operate with a wide range of reference voltages, but signal-to- noise performance is maximized by using as wide a signal range as possible. the recommended refer- ence voltage is 4.5 volts. the cs5101a and cs5102a can actually accept reference voltages up to the positive analog supply. however, the buffer's offset may increase as the reference voltage ap- proaches va+ thereby increasing external drive re- quirements at vref. a 4.5v reference is the maximum reference voltage recommended. this al- lows 0.5v headroom for the internal reference buff- er. also, the buffer enlists the aid of an external 0.1 f ceramic capacitor which must be tied be- tween its output, refbuf, and the negative analog supply, va-. for more information on references, consult application note an004, voltage references for cs5012a / cs5014 /cs5016 / cs5101a / cs5102a / cs5126 series of a/d converters . 6.2 analog input connection the analog input terminal f unctions similarly to the vref input after each c onversion when switching into the track mode. during the first six master clock cycles in the track mode, the buffered version of the analog input is used for coarse-charging the capacitor array. an additional period is required for fine-charging directly from ain to obtain the speci- fied accuracy. figure 12 shows this operation. dur- ing coarse-charge the charge on the capacitor array first settles to the buffered version of the an- alog input. this voltage may be offset from the ac- tual input voltage. during fine-charge, the charge then settles to the accurate unbuffered version. fine-charge settling is specified as a maximum of 1.125 s (cs5101a) or 5.625 s (cs5102a) for an analog source impedance of less than 50 ? . in ad- dition, the comparator requires a source imped- ance of less than 400 ? around 2 mhz for stability. the source impedance can be effectively reduced at high frequencies by adding capacitance from ain to ground (typically 200 pf). however, high dc source resistances will increase the input's rc time constant and extend the necessary acquisi- tion time. for more information on input amplifiers, consult the application note, an006, buffer amplifiers for cs5012a / 14 / 16 / cs5101a / cs5102a / cs5126 series of a/d converters. figure 12. charge settling time 6.3 sleep mode operation the cs5101a and cs5102a include a sleep pin. when sleep is active (low) each device will dissi- pate very low power to retain its calibration memo- 21 20 23 vref refbuf va- 0.1 f 10 f -5v 0.01 f r* +v ee cs5101a or cs5102a ref v r 1 2 c1 c2 + () fpeak ?? () -------------------- --------------------- ---------------------- - = acquisition time (us) internal charge error (lsb's) +200 0 -100 -400 +100 -200 -300 fine-charge coarse-charge 0.25 0.5 0.75 1.0 1.0 2.0 3.0 4.0 8 mhz clock 2.0 mhz clock
cs5101a cs5102a ds45f6 25 ry when the device is not sampling. it does not require calibration after sleep is made inactive (high). when coming out of sleep mode, sampling can begin as soon as the oscillator starts (time will depend on the particular oscillator components) and the refbuf capacitor is charged (which takes about 3 ms for the cs5101a, 50 ms for the cs5102a). to achieve minimum start-up time, use an external clock and leave the voltage reference powered-up. connect a resistor (2 k ? ) between pins 20 and 21 to keep the refbuf capacitor charged. conversion can then begin as soon as the a/d circuitry has stabilized and performed a track cycle. to retain calibration memory while sleep is active (low) va+ and vd+ must be maintained at greater than 2.0v. va- and vd- can be allowed to go to 0 volts. the voltages into va- and vd- cannot just be ?shut-off? as these pins cannot be allowed to float to potentials greater than agnd/dgnd. if the sup- ply voltages to va- and vd- are removed, use a transistor switch to shor t these to the power supply ground while in sleep mode. 6.4 grounding & power supply decoupling the cs5101a and cs5102a use the analog ground connection, agnd, only as a reference voltage. no dc power currents flow through the agnd connection, and it is completely indepen- dent of dgnd. however, any noise riding on the agnd input relative to the system's analog ground will induce conversion errors. therefore, both the analog input and reference voltage should be re- ferred to the agnd pin, which should be used as the entire system's analog ground reference. the digital and analog supplies are isolated within the cs5101a and cs5102a and are pinned out separately to minimize coupling between the ana- log and digital sections of the chip. all four supplies should be decoupled to their respective grounds using 0.1 f ceramic capacitors. if significant low- frequency noise is present on the supplies, tanta- lum capacitors are recommended in parallel with the 0.1 f capacitors. the positive digital power supply of the cs5101a and cs5102a must never exceed the positive an- alog supply by more than a diode drop or the cs5101a and cs5102a could experience perma- nent damage. if the two supplies are derived from separate sources, care must be taken that the an- alog supply comes up firs t at power-up. the sys- tem connection diagram (figure 9) shows a decoupling scheme which allows the cs5101a and cs5102a to be powered from a single set of 5v rails. the positive digital supply is derived from the analog supply through a 10 ? resistor to avoid the analog supply dropping below the digital sup- ply. if this scheme is utilized, care must be taken to ensure that any digital load currents (which flow through the 10 ? resistors) do not cause the mag- nitude of digital supplies to drop below the analog supplies by more than 0.5 volts. digital supplies must always remain above the minimum specifica- tion. as with any high-precision a/d converter, the cs5101a and cs5102a require careful attention to grounding and layout arrangements. however, no unique layout issues must be addressed to properly apply the devices.
cs5101a cs5102a 26 ds45f6 7. cs5101a & cs5102a performance 7.1 differential nonlinearity the self-calibration scheme utilized in the cs5101a and cs5102a features a calibration res- olution of 1/4 lsb, or 18-bits. this ideally yields dnl of 1/4 lsb, with code widths ranging from 3/4 to 5/4 lsbs. traditional laser-trimmed adcs have significant differential nonlinearities. appearing as wide and narrow codes, dnl often causes entire sections of the transfer function to be missing. although their affect is minor on s/(n+d) with high amplitude sig- nals, dnl errors dominate performance with low- level signals. for instance, a signal 80 db below full-scale will slew past only 6 or 7 codes. half of those codes could be missing with a conventional 16-bit adc which achieves only 14-bit dnl. the most common source of dnl errors in con- ventional adcs is bit weight errors. these can arise due to accuracy limitations in factory trim sta- tions, thermal or physical st resses after calibration, and/or drifts due to aging or temperature variations in the field. bit-weight errors have a drastic effect on a converter's ac performance. they can be an- alyzed as step functions superimposed on the in- put signal. since bits (and their errors) switch in and out throughout the transfer curve, their effect is signal dependent. that is, harmonic and inter- modulation distortion, as well as noise, can vary with different input conditions. differential nonlinearities in successive-approxi- mation adcs also arise due to dynamic errors in the comparator. such errors can dominate if the converter's throughput/sampling rate is too high. the comparator will not be allowed sufficient time to settle during each bit decision in the successive- approximation algorithm. the worst-case codes for dynamic errors are the major transitions (1/2 fs; 1/4, 3/4 fs; etc.). since dnl effects are most crit- ical with low-level signal s, the codes around mid- scale (1/2 fs) are most important. yet those codes are worst-case for dynamic dnl errors! with all linearity calibration performed on-chip to 18-bits, the cs5101a and cs5102a maintain ac- curate bit weights. dnl errors are dominated by residual calibration errors of 1/4 lsb rather than dynamic errors in the comparator. furthermore, all dnl effects on s/(n+d) are buried by white broad- band noise. (see figures 19 and 21). figure 13 illustrates the dnl histogram plot of a typical cs5101a at 25 c. figure 14 illustrates the dnl of the cs5101a at 138 c ambient after cali- bration at 25 c ambient. figure 15 and figure 16 illustrate the dnl of the cs5102a at 25 c and 138 c ambient, respectively. a histogram test is a statistical method of deriving an a/d converter's differential nonlinearity. a ramp is input to the a/d and a large number of samples are taken to ensure a high confidence level in the test's result. the number of occurrences for each code is monitored and stored. a perfect a/d converter would have all codes of equal size and therefore equal numbers of occurrences. in the histogram test a code with the average number of occurrences will be consid- ered ideal (dnl = 0). a code with more or less oc- currences than average will appear as a dnl of greater or less than zero lsb. a missing code has zero occurrences, and will appear as a dnl of -1 lsb. figures 17 and 18 illustrate the code width distribu- tion of the dnl plots shown in figure 13 and figure 15 respectively. t he dnl error distribution plots indicate that the cs5101a and cs5102a cal- ibrate the majority of their codes to tighter toler- ance than the dnl plots in figures 13 and 15 appear to indicate.
cs5101a cs5102a ds45f6 27 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 25 c 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 138 c, cal @ 25 c 0 65,535 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 25 c 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 t a = 138 c, cal @ 25 c figure 13. cs5101a dnl plot - ambient temperature at 25 c figure 14. cs5101a dnl plot - ambient temperature at 138 c figure 15. cs5102a dnl plot - ambient temperature at 25 c figure 16. cs5102a dnl plot - ambient temperature at 138 c codes
cs5101a cs5102a 28 ds45f6 figure 17. cs5101a dnl error distribution figure 18. cs5102a dnl error distribution 7.2 fft tests and windowing in the factory, the cs5101a and cs5102a are tested using fast fourier transform (fft) tech- niques to analyze the conv erters' dynamic perfor- mance. a pure sine wave is applied to the device, and a ?time record? of 1024 samples is captured and processed. the fft algorithm analyzes the spectral content of the digital waveform and distrib- utes its energy among 512 ?frequency bins.? as- suming an ideal sine wave, distribution of energy in bins outside of the fundamental and dc can only be due to quantization effects and errors in the cs5101a and cs5102a.
cs5101a cs5102a ds45f6 29 figure 19. cs5101a fft (ssc mode, 1-channel) figure 20. cs5101a fft (ssc mode, 1-channel) figure 21. cs5102a fft (ssc mode, 1-channel) figure 22. cs5102a fft (ssc mode, 1-channel) if sampling is not synchronized to the input sine wave, it is highly unlikely that the time record will contain an integer number of periods of the input signal. however, the fft assumes that the signal is periodic, and will calculat e the spectrum of a sig- nal that appears to have large discontinuities, thereby yielding a severely distorted spectrum. to avoid this problem, the time record is multiplied by a window function prior to performing the fft. the window function smoothly forces the endpoints of the time record to zero, thereby removing the dis- continuities. the effect of the window in the frequency-domain is to convolute the spectrum of the window with that of the actual input. the quality of the window used for harmonic anal- ysis is typically judged by its highest side-lobe lev- el. a five term window is used in fft testing of the cs5101a and cs5102a. this windowing algo- rithm attenuates the side-lobes to below the noise floor. artifacts of windowing are discarded from the signal-to-noise calculation using the assumption that quantization noise is white. averaging the fft results from ten time records filters the spectral variability that can arise from capturing finite time records without disturbing the total energy outside the fundamental. all harmonics are visible in the plots. as illustrated in figure 19, the cs5101a typically provides about 92 db s/(n+d) and 0.001% thd at 25 c. figure 20 illustrates only minor degradation in performance when the ambient temperature is raised to 138 c. figures 21 and 22 illustrate that the cs5102a typically yields 92 db s/(n+d) and 0.001% thd even with a large change in ambient temperature. unlike c onventional successive-ap- proximation adc's, the signal-to-noise and dy- namic range of the cs5101a and cs5102a are
cs5101a cs5102a 30 ds45f6 not limited by differential nonlinearities (dnl) caused by calibration errors. rather, the dominant noise source is broadband thermal noise which aliases into the baseband. this white broadband noise also appears as an idle channel noise of 1/2 lsb (rms). 7.3 sampling distortion like most discrete sample/hold amplifier designs, the inherent sample/hold of the cs5101a and cs5102a exhibits a frequency-dependent distor- tion due to non-ideal sampling of the analog input voltage. the calibrated capacitor array used during conversions is also used to track and hold the an- alog input signal. the conversion is not performed on the analog input voltage per se, but is actually performed on the charge trapped on the capacitor array at the moment the hold command is given. the charge on the array ideally assumes a linear relationship to the analog input voltage. any devia- tion from this linear relati onship will result in con- version errors even if the conversion process proceeds flawlessly. at dc, the dac capacitor array's voltage coeffi- cient dictates the conver ter's linearity. this varia- tion in capacitance with respect to applied signal voltage yields a nonlinear relationship between the charge on the array and the analog input voltage and places a bow or wave in the transfer function. this is the dominant source of distortion at low in- put frequencies (figures 19, 20, 21, and 22). the ideal relationship between the charge on the array and the input voltage can also be distorted at high signal frequencies due to nonlinearities in the internal mos switches. dynamic signal s cause ac current to flow through the switches connecting the capacitor array to the analog input pin in the track mode. nonlinear on-resistance in the switches causes a nonlinear voltage drop. this effect wors- ens with increased signal frequency and slew rate. this distortion is negligible at signal levels below - 10 db of full scale.
cs5101a cs5102a ds45f6 31 figure 23. cs5101a histogram plot of 8192 conversion inputs figure 24. cs5102a histogram plot of 8192 conversion inputs 7.4 noise an a/d converter's noise can be described like that of any other analog component. however, the con- verter's output is in digital form so any filtering of its noise must be performed in the digital domain. dig- itized samples of analog inputs are often consid- ered individual, static snap-shots in time with no uncertainty or noise. in reality, the result of each conversion depends on the analog input level and the instantaneous value of noise sources in the adc. if sequential samples from the adc are treated as a ?waveform?, simple filtering can be im- plemented in software to improve noise perfor- mance with minimal processing overhead. all analog circuitry in the cs5101a and cs5102a is wideband in order to achieve fast conversions and high throughput. wideband noise in the cs5101a and cs5102a integrates to 35 v rms in unipolar mode (70 v rms in bipolar mode). this is approximately 1/2 lsb rms with a 4.5v reference in both modes. figure 23 shows a histogram plot of output code occurrences obtained from 8192 sam- ples taken from a cs5101a in the bipolar mode. hexadecimal code 7ffe was arbitrarily selected and the analog input was set close to code center. with a noiseless conver ter, code 7ffe would al- ways appear. the histogram plot of the device has a ?bell? shape with all codes other than 7ffe due to internal noise. figure 24 illustrates the noise his- togram of the cs5102a. in a sampled data system all information about the analog input applied to the sample/hold appears in the baseband from dc to one-half the sampling rate. this includes high-frequency components which alias into the baseband. low-pass (anti- alias) filters are therefore used to remove frequen- cy components in the input signal which are above one-half the sample rate. however, all wideband noise introduced by the cs5101a and cs5102a still aliases into the baseband. this ?white? noise is evenly spread from dc to one-half the sampling rate and integrates to 35 v rms in unipolar mode. noise in the digital domain can be reduced by sam- pling at higher than the desired word rate and av- eraging multiple samples for each word. oversampling spreads the device's noise over a wider band (for lower noise density), and averag- ing applies a low-pass response which filters noise above the desired signal bandwidth. in general, the device's noise performance can be maximized in any application by always sampling at the maxi- mum specified rate of 100 ksps (cs5101a) or 20 ksps (cs5102a) (for lowest noise density) and digitally filtering to the desired signal bandwidth. 7.5 aperture jitter track-and-hold amplifiers commonly exhibit two types of aperture jitter. the first, more appropriate- ly termed ?aperture window?, is an input-voltage- dependent variation in the aperture delay. its sig- nal dependency causes distortion at high frequen- 7ffc 7ffd 7ffe 8000 8001 7fff 7ffb 2048 4096 6144 8192 count noiseless cs5101a code (hexadecimal) counts: 0 0 989 6359 844 0 0 converter 7ffe 7fff 8000(h) 8002 8003 8001 7ffd count noiseless cs5102a code (hexadecimal) counts: 05 1727 4988 1467 5 0 converter 8192 6144 4096 2048
cs5101a cs5102a 32 ds45f6 cies. the proprietary architecture of the cs5101a and cs5102a avoids applying the input voltage across a sampling switch, thus avoiding any ?aper- ture window? effects. the second type of aperture jitter, due to component noise, assumes a random nature. with only 100 ps peak-to-peak aperture jit- ter, the cs5101a and cs5102a can process full- scale signals up to 1/2 the throughput frequency without significant errors due to aperture jitter. figure 25. power supply rejection 7.6 power supply rejection the power supply rejection performance of the cs5101a and cs5102a is enhanced by the on- chip self-calibration and an ?auto-zero? process. drifts in power supply voltages at frequencies less than the calibration rate have negligible effect on the device's accuracy. this is because the cs5101a and cs5102a adjust their offset to within a small fraction of an lsb during calibration. above the calibration frequency the excellent power sup- ply rejection of the internal amplifiers is augmented by an auto-zero process. any offsets are stored on the capacitor array and are effectively subtracted once conversion is initiated. figure 25 shows pow- er supply rejection of the cs5101a and cs5102a in the bipolar mode with the analog input grounded and a 300 mv p-p ripple applied to each supply. power supply rejection improves by 6 db in the un- ipolar mode. power supply ripple frequency power supply rejection (db) 90 80 70 60 50 40 30 20 1 khz 10 khz 100 khz 1 mhz
cs5101a cs5102a ds45f6 33 8. pin descriptions figure 26. cs5101a & cs5102a 28-pin plcc pinout 8.1 power supply connections vd+ - positive digital power, pin 7 positive digital power supply. nominally +5 volts. vd- - negative digital power, pin 1. negative digital power supply. nominally -5 volts. dgnd - digital ground, pin 6. digital ground [reference]. va+ - positive analog power, pin 25. positive analog power supply. nominally +5 volts. va- - negative analog power, pin 23. negative analog power supply. nominally -5 volts. agnd - analog ground, pin 22. analog ground reference. vref refbuf agnd va- ain2 va+ ain1 crs/fin trk2 trk1 vd+ dgnd stby ssh/sdl sckmod sleep vd- rst clkin xout test bp/up code sdata sclk ch1/2 hold outmod 10 9 8 7 6 5 11 20 21 22 23 24 25 19 17 16 15 14 13 12 18 27 28 1 2 3 4 26 cs5101a cs5102a (top view)
cs5101a cs5102a 34 ds45f6 8.2 oscillator clkin - clock input, pin 3. all conversions and calibrations are timed from a master clock which can be externally supplied by driving clkin [this input ttl- compatible, cmos recommended]. xout - crystal output, pin 4. the master clock can be generated by tying a crystal across the clkin and xout pins. if an external clock is used, xout must be left floating. 8.3 digital inputs hold - hold, pin 12. a falling transition on this pin sets the cs5101a or cs5102a to the hold state and initiates a conversion. this input must remain low for at least 1/tclk + 20 ns. when operating in free run mode, hold is disabled, and should be tied to dgnd or vd+. crs/fin - coarse charge/fine charge control, pin 10. when brought high during acquisition time, crs/fin forces the cs5101a or cs5102a into coarse charge state. this engages the internal buffer am plifier to track the analog input and charges the capacitor array much faster, thereby allowing the cs5101a or cs5102a to track high-slewing signals. in order to get an accurate sample, th e last coarse charge period before initiating a conversion (bringing hold low) must be longer than 0.75 s (cs5101a) or 3.75 s (cs5102a). similarly, the fine charge period immediately prior to c onversion must be at least 1.125 s (cs5101a) or 5.625 s (cs5102a). the crs/fin pin must be low during conversion time. for normal operation, crs/fin should be tied low, in which case the cs5101a or cs5102a will automatically enter co arse charge for 6 clock cycles immediately after the end of conversion. ch1/2 - left/right input ch annel select, pin 13. status at the end of a conversion cycle determines whic h analog input channel will be acquired for the next conversion cycle. when in free run mode, ch1/2 is an output, and will indicate which channel is being sampled during the current acquisition phase. sleep - sleep, pin 28. when brought low causes the cs5101a or cs5102 a to enter a power-down state. all calibration coefficients are retained in memory, so no recalibration is needed after returning to the normal operating mode. if using the in ternal crystal oscillator, time must be allowed after sleep returns high for the crystal oscillator to stabilize. sleep should be tied high for normal operation. code - 2's complement/binary coding select, pin 16. determines whether output data appears in 2's comple ment or binary format. if high, 2's complement; if low, binary. bp/up - bipolar/unipol ar input range select, pin 17. when low, the cs5101a or cs5102a accepts a unipolar input range from agnd to vref. when high, the cs5101a or cs5102a accepts bipolar inputs from -vref to +vref. sckmod - serial clock mode select, pin 27. when high, the sclk pin is an input; when low, it is an output. used in conjunction with outmod to select one of 4 output modes described in table 2. outmod - output mode select, pin 18. the status of sckmod and outmod determine which of four output modes is utilized. the four modes are described in table 2.
cs5101a cs5102a ds45f6 35 sclk - serial clock, pin 14. serial data changes status on a falling edge of this input, and is valid on a rising edge. when sckmod is high sclk acts as an inpu t. when sckmod is low the cs5101a or cs5102a generates its own serial clock at ? the master clock frequency and sclk is an output. rst - reset, pin 2. when taken low, all internal digital logic is reset. upon returning high, a full calibration sequence is initiated which takes 11,528,160 clkin cycles (cs5101a) or 2,882,040 clkin cycles (cs5102a) to complete. during ca libration, the hold input will be ignored. the cs5101a or cs5102a must be reset at power-up for calibration, however; calibration is maintained during sleep mode, and need not be repeated when resuming normal operation. 8.4 analog inputs ain1, ain2 - channel 1 and 2 analog inputs, pins 19 and 24. analog input connections for the left and right input channels. vref - voltage reference, pin 20. the analog reference voltage which sets the analog input range. in unipolar mode vref sets full-scale; in bipolar mode its magnitude sets both positive and negative full-scale. 8.5 digital outputs stby - standby (calibrating), pin 5. indicates calibration status after reset. remains low throughout the calibration sequence and returns high upon completion. sdata - serial output, pin 15. presents each output da ta bit on a falling edge of sclk. data is valid to be latched on the rising edge of sclk. ssh/sdl - simultaneous sample/hol d / serial data latch, pin 11. used to control an external sample/hold amplifier to achieve simultaneous sampling between channels. in frn and ssc modes (sclk is an out put), this signal provides a conv enient latch signal which forms the 16 data bits. this can be used to control external se rial to parallel latches, or to control the serial port in a dsp. trk1 , trk2 - tracking channel 1, tracking channel 2, pins 8 and 9. falls low at the end of a conversion cycle, indi cating the acquisition phase for the corresponding channel. the trk1 or trk2 pin will return high at the beginni ng of conversion for that channel. 8.6 analog outputs refbuf - reference bu ffer output, pin 21. reference buffer output. 8.7 miscellaneous test - test, pin 26. allows access to the cs5101a's and the cs5102a's te st functions which are reserved for factory use. must be tied to vd+.
cs5101a cs5102a 36 ds45f6 9. parameter definitions linearity error the deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. ?zero-scale? is a point 1/2 lsb below the first code transition and ?full-scale? is a point 1/2 lsb beyond t he code transition to all ones. the deviation is mea- sured from the middle of each particular code. units in % full-scale. differential linearity minimum resolution for which no missing codes is guaranteed. units in bits. full-scale error the deviation of the last code transition from the ideal (vref-3/2 lsbs). units in lsbs. unipolar offset the deviation of the first code transition from t he ideal (1/2 lsb above agnd) when in unipolar mode (bp/up low). units in lsbs. bipolar offset the deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 lsb below agnd) when in bipolar mode (bp/up high). units in lsbs. bipolar negative full-scale error the deviation of the first code transi tion from the ideal when in bipolar mode (bp/up high). the ideal is defined as lying on a straight line which passes thro ugh the final and mid-scale co de transitions. units in lsbs. signal-to-peak harmonic or noise the ratio of the rms value of the signal to the rms value of the next largest spectral component below the nyquist rate (excepting dc). this component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. expressed in decibels. total harmonic distortion the ratio of the rms sum of all harmonics to the rms value of the signal. units in percent. signal-to-(noise + distortion) the ratio of the rms value of the signal to the rms sum of all other spectral components below the nyquist rate (excepting dc), including distortion components. expressed in decibels. aperture time the time required after the hold command for the sampling switch to open fully. effectively a sampling delay which can be nulled by advancing the sampling signal. units in nanoseconds. aperture jitter the range of variation in the aperture time. effectivel y the ?sampling window? which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. units in picoseconds.
cs5101a cs5102a ds45f6 37 10. package dimensions figure 27. 28-pin plcc mechanical drawing inches millimeters dim min nom max min nom max a 0.165 0.1725 0.180 4.191 4.3815 4.572 a1 0.090 0.105 0.120 2.286 2.667 3.048 b 0.013 0.017 0.021 0.3302 0.4318 0.533 d 0.485 0.490 0.495 12.319 12.446 12.573 d1 0.450 0.453 0.456 11.430 11.506 11.582 d2 0.390 0.410 0.430 9.906 10.414 10.922 e 0.485 0.490 0.495 12.319 12.446 12.573 e1 0.450 0.453 0.456 11.430 11.506 11.582 e2 0.390 0.410 0.430 9.906 10.414 10.922 e 0.040 0.050 0.060 1.016 1.270 1.524 jedec # : ms-047 aa-af controlling dimension is inches 28l plcc package drawing d1 d e1 e d2/e2 b e a1 a
cs5101a cs5102a 38 ds45f6 11. ordering information 12. environmental, manufactur ing, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model linearity temperature conversion time throughput package cs5101a-jl8 0.003 0 to +70 c 8.13 s 100 ksps 28-pin plcc cs5101a-jl8z (lead free) cs5101a-bl8 0.002 -40 to +85 c CS5101A-BL8Z (lead free) cs5102a-jl 0.003 0 to +70 c 40 s20 ksps cs5102a-jlz (lead free) cs5102a-bl 0.0015 -40 to +85 c cs5102a-blz (lead free) model number peak reflow temp msl rating* max floor life cs5101a-jl8 225 c 2365 days cs5101a-jl8z (lead free) 260 c cs5101a-bl8 225 c CS5101A-BL8Z (lead free) 260 c cs5102a-jl 225 c cs5102a-jlz (lead free) 260 c cs5102a-bl 225 c cs5102a-blz (lead free) 260 c
cs5101a cs5102a ds45f6 39 13. revisions revision date changes f1 september 2004 initial release f2 october 2004 corrected table heading on page 6. f3 june 2005 minor edits, added lead-free device ordering information f4 july 2005 removed obsolete packages, corrected lead-free device information f5 august 2005 added msl, reflow temp, & floor life specifications. f6 january 2006 corrected linearity error mislabeled in characteristics & specifications as ?dif- ferential input range?. contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject t o change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtai n the latest version of relevant info r mation to verify, before placing orders, that information being relied on is current and complete. all products are sold subjec t to the terms and conditions of sale supplie d at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no r esponsibility is assumed by cirrus for th e use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringeme nt of patents or other rights of third partie s this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyright s trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information con tained herein and gives consent for copie s to be made of the information only for use within your organization with respect to cirrus integrated circuits or other product s of cirrus. this consent does not exten d to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for re sale. certain applications us ing semiconductor products may invo lve potential risks of death, personal injury, or severe prope r ty or environmental damage (? critical applications?). cirrus products are not designed, auth orized or warranted for use i n aircraft systems, military applications, products surgically implanted into the body, automotive safety or security device s life support products or other cr itical applications. inclusio n of cirrus products in such appl ications is u nderstood to b e fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implie d warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer us es or permits the use of cirrus prod ucts in critical app lications, custo m er agrees, by such use, to fully indemnif y cirrus, its officers, directors, employees, distributors and other agents from an y and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are tradem arks of cirrus logic, inc. all other brand and product names in this document may be trademarks o service marks of their respective owners.

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